- "The MDK hashboard uses 100x Intel Blockscale 1000 Series™ ASICs in a gridlike array. This ASIC count ensures the MDK board, in a standard three-board chassis format, will have a power footprint compatible with the widely available APW12 power supply."
- "The hashboard is also sized to be compatible with popular miner chassis dimensions. It has thus been designed to allow easy use of aftermarket components. Some photos of our prototype hashboard are provided below."
- "In order to keep temperatures under control and maintain operational steady state, aluminum heatsinks are attached to the board and make contact with each ASIC using a highly conductive Thermal Interface Material (TIM)."
"Once launched into the market next year, we hope to see the MDK hashboard employed in a variety of emerging mining use cases including heat re-use and stranded power applications, as well as in traditional industrial mining."
- "As part of this, we'd love to see the MDK used to explore innovative, sustainable energy applications for mining. We also hope our transparent and open source approach offers a material practical improvement for developers looking to work on novel mining applications."
- "Given the primary intent to support development, we are including more features in the MDK hashboard than exist on most commercial mining hashboards and welcome all developer feedback regarding which are most valuable and should remain in our future mining systems."
- Distributed controller architecture. "We opted to place a microcontroller on the hashboard itself, allowing local processing of certain functions. This allows novel, flexible architectures to be supported."
- Precision load control. We have introduced components on the hashboard to support fine-grained modulation of the power consumption of the hashboard. This will allow rapid startup of hashing from miner power off or sleep mode, including in environments with low ambient temperatures.
- Extended operating range. Facilitated by our software, the board is capable of operating across a very wide range of power and efficiency, limited only by thermal dissipation capacity at the upper end and the ASIC minimum clock speeds at the lower end.
- On-chip temperature monitoring. "We will be able to shut down hashing operations before the ASICs reach temperature levels that might damage them."
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